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The Test Technology Technical Council supports the development and maintenance of the following IEEE standards:

An overview of Test Technology standards:

  • IEEE 1149.1:
  • Test Access Port and Boundary-Scan
    Christopher J. CLARK, Cclark-at-intellitech-dot-com
  • IEEE 1149.4:
  • Mixed Signal Test Bus
    Bambang SUPARJO,
  • IEEE 1149.6:
  • Boundary Scan Testing of Advanced Digital Networks
    Bill EKLOW,
  • IEEE P1149.7:
  • Standard for Reduced-pin and Enhanced-functionality Test Access Port and Boundary Scan Architecture
    Robert OSHANA,
  • IEEE 1450-1999:
  • Standard Tester Interface Language (STIL)
    Gregory MASTON,
  • IEEE 1450.1:
  • Extensions to STIL for Semiconductor Design Environment
    Tony TAYLOR,
  • IEEE 1450.2-2002:
  • Extensions to STIL for DC Level Specification
    Gregg WILDER,
  • IEEE P1450.3:
  • Extensions to STIL for Tester Target Specification
    Tony TAYLOR,
  • IEEE P1450.4:
  • Extensions to STIL for Test Flow Specification
    Doug SPRAGUE,
    Jim O'REILLY,
  • IEEE P1450.6-1:
  • Standard for Describing On-Chip Scan Compression
    Bruce CORY,
  • IEEE P1450.6-2:
  • Standard for Memory Modeling in Core Test Language (CTL)
    Saman ADHAM,
  • IEEE 1450.6-2005:
  • Extensions to STIL for Core Test Language (CTL) Support
    Rohit KAPUR,
  • IEEE P1450.7:
  • Extensions to STIL for Analog and Mixed Signal Environments
    Jean-Louis CARBONERO,
  • IEEE 1500:
  • Embedded Core Test
    Yervant ZORIAN,
  • IEEE 1532:
  • In-System Configuration of Programmable Devices
    Neil JACOBSON,
  • IEEE P1581:
  • Static Component Interconnection Test Protocol and Architecture (SCITT)
    Heiko EHRENBERG,
  • IEEE P1687:
    Kenneth POSSE,
    Alfred CROUCH,
  • IEEE P1838:
  • Test Access Architecture for Three-Dimensional Stacked Integrated Circuits
    Erik Jan Marinissen,

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    This page last updated: Nov. 18, 2013  —
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